At-Speed Scan Test in ASIC Design with On-Chip Clock

XIN HE, WU YANG, JUN DENG, KE-LIU HU, TAO ZHANG, YI-RU FU

Abstract


With the gradual improvement of clock frequency of large scale integrated circuits, the traditional stuck-at fault testing method cannot meet the requirements of chip test quality. Firstly, this paper introduces the fault model of at-speed test, the structure of on-chip clock control and the specific test method. Secondly, it introduces the at-speed test implementation of a chip in detail, when PLL clock is used as at-speed test clock .Finally, TetraMAX is used to automatically generate test vectors and vector compression for the whole design. The experimental results show that the scheme is feasible and the compression design of test vectors is more suitable for the current design requirements.

Keywords


At-speed Test, DFT, ATPGText


DOI
10.12783/dtetr/ecae2018/27741

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