An Effective Method for Interconnect Delay Optimization of ASIC’s

XU HUANG, KUN LIU, XIAO-ZONG HUANG, ZHENG-RONG HE

Abstract


With the development of integrated circuit design into 65nm process, interconnect delay has become one of the key factors that hinder the convergence of time sequence. Firstly, the determinants of interconnect delay are analyzed by Elmore delay model, and then experiments are carried out at the stage of circuit physical design. Verify the metal layer, metal width, buffer driving ability and buffer number can effectively optimize the interconnect delay.

Keywords


Interconnect delay, Buffers insertion, Timing optimizationText


DOI
10.12783/dtetr/ecae2018/27740

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