Using UVM Testbench to Generate the Analog Stimuli

Xu HUANG, Xin HE, Zheng-rong HE, Xiao-zong HUANG


In an environment for verifying digital designs, constrained random verification is employed to create lots of scenarios that help to uncover deep-rooted bugs in the design. Analog blocks such as Analog-to-Digital Converters (ADC), voltage regulators need a similar kind of verification environment to ensure the quality of design. Effects of noise on supply, abrupt changes in voltage sources have to be observed to evaluate the performance of the design. Self-checking and highly automated testbenches generating analog stimuli are required for this purpose. In this paper we present an approach to drive analog stimuli to the Design-Under-Test (DUT) from a SystemVerilog testbench based on Universal Verification Methodology (UVM). Verilog-AMS models were developed for the analog components in the DUT.


Analog stimuli, Universal Verification Methodology, Constrained Random Verification.


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