A Hardware Structure for FAST Protocol Decoding Adapting to 40Gbps Bandwidth

Lei-Lei YU, Yu-Zhuo FU, Ting LIU

Abstract


FAST protocol is a kind of Data Compression Protocols which is widely used in Highfrequency trading. So far, implements of fast protocol decoding mainly depend on software. On the other hand, transmission delay of decoding can be effectively decreased by customized hardware instead of software. However, most of FPGA hardware architectures are serial. A parallel FPGA hardware structure for fast protocol decoding adapting to 40Gbps bandwidth is proposed in this paper. The structure includes 3 modules: field dividing module, field matching module and parallel decoding units. The practicability and efficiency of the proposed architecture is verified in System C platform and it takes 173ns to decode a message whose field number is 64. At last, influence of three factors to transmission delay is discussed in this paper, including decoding unit number, field type and sequence length of message.

Keywords


FAST protocol, Decoding, FPGA, 40Gbps bandwidth


DOI
10.12783/dtcse/csma2017/17357

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